The present invention relates to a JFET transistor whose pinch-off voltage can be set by layout measures.
Depending on the specific requirements to be fulfilled by a transistor, a JFET transistor may be preferable to a MOS transistors. Thus, for instance, a JFET transistor has a lower noise than a MOS transistor because the current flow through a JFET transistor is not caused by surface effects but occurs "in the depth" below the surface of the substrate.
The state of the art includes JFET transistors configured according to FIGS. 1-3 and produced in CMOS technology. A p-substrate 1 having a surface 2 is provided, by way of diffusion, with an n-well 3 therein which in turn has a p-well 4 embedded therein. Arranged in this p-well 4 are source and drain electrode regions 5,6 with a degenerate p-doping, having arranged therebetween a gate electrode region 7 with a degenerate n-doping. As evident from the systematic view of FIG. 3, the gate electrode region 7 extends in the manner of a web transversely across the p-well 4 and into the n-well 3 in which the gate electrode region is formed as an annular region 8 surrounding the p-well 4. The adjacent region of the surface 2 of the p-substrate 1 arranged external of this annular region 8 is covered by field oxide 9.
In the example of a known JFET transistor illustrated in FIGS. 1-3, the p-well 4 forms the channel of the JFET transistor (p-channel JFET transistor). The control of the channel and thus the control of the current flow takes place via the space-charge zone between the gate electrode region 7 and the p-well 4 which in comparison with this electrode region has a considerably weaker doping. As a result of the selected doping material concentrations, this space-charge zone is generated for the most part in the p-well 4.
By the above configuration, it is accomplished that
the transistor is insulated from the p-substrate by two p-n-transitions, and the substrate potential will thus have no effects on the transistor parameters and particularly on the pinch-off voltage, and PA1 the JFET transistor has a lower noise because of the channel extending below the silicon surface. PA1 In an existing n-well CMOS-process, it becomes necessary to introduce an additional p-well along with a complete change of the beginning of the process (well diffusion/field oxidation/temperature balance). PA1 When using epitaxial substrates, the penetration depth of the n-well is limited by the outdiffusion of the substrate doping. PA1 In a diffused p-well, the surface concentration (voltage sustaining capability of the gate electrode) and the doping profile in the depth (conductivity of the channel) are coupled with each other. PA1 The diffusion depth of the gate electrode is to be exactly adapted to the desired pinch-off voltage and must be controlled. PA1 The pinch-off voltage of the transistor is fixedly determined by the diffusion depths and profiles set in the process. PA1 An adaptation of the well doping/diffusions will at the same time have an influence on nearly all other constructional components. PA1 a semiconductive substrate, PA1 a channel well region of a first conductive type formed in the substrate, PA1 a source and a drain electrode region of the first conductive type which are arranged in a mutually spaced relationship in the channel well region, PA1 a gate electrode region of a second conductive type opposite to the first conductive type, extending between the source and drain electrode regions through the channel well region into the region of the substrate surface external of the channel well region, wherein said region and the rest of the surrounding region of the substrate laterally of and below the channel well region is doped with charge carriers of the second conductive type, and wherein, below the gate electrode region, a channel region is formed within the channel well region, with the cross section of said channel region being controllable by means of space-charge zones formed in the transition regions between the gate electrode region and the channel well region. PA1 below the gate electrode region, a plurality of partial regions of the second conductive type are arranged next to each other in the direction of the extension of the gate electrode region and in a mutually spaced relationship, said partial regions bordering on the gate electrode region and extending through the channel well region into the region of the substrate bordering on the channel well region from below.
The above advantages require suitable wells 3,4, wherein the n-well 3 must be significantly deeper than the p-well 4 to obtain the necessary insulating characteristics and voltage sustaining capabilities. For setting the desired pinch-off voltage, there are required, on the one hand, an exactly defined depth of the gate electrode region 7 and, on the other hand, an exact depth of the p-well 4 as well as an exactly set doping material concentration in the p-well 4.
An integration of the known construction into an existing CMOS process requires a considerable process expenditure, notably for the following reasons:
As evident from the above, it is only by changing the process parameters (diffusion depth of the gate electrode region and depth of p-well 4) that the pinch-off voltage JFET transistor can be influenced. In an existing CMOS process, however, it is highly undesirable to change the process parameters of individual process steps for individual components.
Thus, it is an object of the invention to provide a JFET transistor which can be produced in CMOS technology without the need to change the process parameters for setting the pinch-off voltage.